Training Courses |
Verilog for SynthesisCourse id: 0020 SynopsisField Programmable Gate Arrays have allowed engineers to develop complex, sophisticated and extremely fast digital systems. Due to their versatility, they are also by far the most feasible option for prototyping. The complexity of digital systems however, meant it is more than necessary to develop such systems in hardware description languages (HDL) rather than schematic capture.
This course introduces the complete FPGA development flow and environment with Verilog HDL. The emphasis here is on the subset of Verilog that is synthesizable -- i.e. capable of producing hardware -- rather than the entire HDL. Proper, generic hardware description style and implementation techniques are introduced throughout the course.
Course highlight
Participants will have practical design experience using the Altera DE2 FPGA development board, together with the use of Altera's Quartus II development software and Mentor Graphic's ModelSim-Altera simulator. What participants say about the course
The following are some verbatim statements from the participants: - The instructor try to do his best to make me understand this course using hardware and software -- Dec 2009
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The instructor patiently try to make me understand when I don't understand -- Dec 2009
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Improved my skills and give a lot of benefit to my future work -- Jan 2010
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Learn hands-on about programming a design using software and hardware, the lecturer also nice and knowledgeable about the course and make the class live -- Jan 2010
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An opportunity for me to learn a new software tool in playing with verilog HDL by using Quartus II -- Jul 2011
What you will learnThis course concentrates on the theoretical and practical knowledge to allow participants to achieve the following learning outcomes. Upon completing the course, participants would be able to:
- Familiarise with Altera's Quartus II and Graphics's ModelSim for design entry, analysis and simulation
- Know the fundamentals of Verilog, with particular emphasis on synthesizable constructs (i.e. able to generate hardware)
- Describe combinational and sequential circuits in a structural and behavioral manner
- Develop digital systems in a hierarchical and modular nature to aid testing, debugging and hardware reuse
- Learn and use Verilog constructs for simulation and verification with testbenches
- Describe the operation of sequential circuits in the Register Transfer Level (RTL) notation
- Describe control flow with Algorithmic State Machines (ASM) and implement them in Verilog
Who should attendThis course is particularly suited for engineers involved in digital design and testing who are new to the HDL flow.PrerequisiteParticipants should have a diploma/degree in electronics (and related) engineering with an understanding of digital systems. This course is the recommended prerequisite for the "Advanced Synthesis with Verilog" course.Course methodologyThis course is presented in a workshop style with example-led lectures interlaced with hands-on practical for maximum understanding.Course duration4 days.Course structure
- Introduction
- HDL design flow
- History of Verilog
- Structural HDL
- Behavioral HDL description
- Hands-on Practical 1: Introduction to Quartus II
- Basic Verilog 1
- Language constructs
- Data types and representation
- Component instantiation
- Concurrent statements
- Operators
- Multiplexers
- Hands-on Practical 2: Combinational Logic
- Basic Verilog 2
- Concatenation
- Repetition
- Aggregates and array slices
- Enumeration
- RAMs and ROMs
- Hands-on Practical 3: Seven Segment Decoder
- Sequential Design
- Register basics
- Sequential statements
- Blocking assignments
- Registers, latches and counters
- Hands-on Practical 4: Up/Down Counter
- Modularisation
- Hierarchical design
- Parameterization
- Generation
- Hands-on Practical 5: Real-time Clock
- State Machine
- Registers transfer operations
- Algorithmic State Machine
- Hands-on Practical 6: Serial Transceiver (Transmission)
- Testbenches
- Introduction
- Testbench methods
- Hands-on Practical 7: ModelSim-Altera Simulations
- Hands-on Practical 8: Serial Transceiver (Reception)
InstructorDr Royan Ong
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