Training Courses

VHDL for Synthesis

Course id: 0021

Synopsis

This course introduces the complete FPGA development flow and environment with VHDL. The emphasis here is on the subset of VHDL that is synthesizable -- i.e. capable of producing hardware -- rather than the entire HDL. Proper, generic hardware description style and implementation techniques are introduced throughout the course.

Course highlight Participants will have practical design experience using the Altera DE2 FPGA development board, together with the use of Altera's Quartus II development software and Mentor Graphic's ModelSim-Altera simulator.

This course is similar to the Verilog for Synthesis course.

What you will learn

• Familiarise with Altera's Quartus II and Graphics's ModelSim for design entry, analysis and simulation
• Know the fundamentals of VHDL, with particular emphasis on synthesizable constructs (i.e. able to generate hardware)
• Describe combinational and sequential circuits in a structural and behavioral manner
• Develop digital systems in a hierarchical and modular nature to aid testing, debugging and hardware reuse
• Learn and use VHDL constructs for simulation and verification with testbenches
• Describe the operation of sequential circuits in the Register Transfer Level (RTL) notation
• Describe control flow with Algorithmic State Machines (ASM) and implement them in VHDL

Who should attend

Prerequisite

Course methodology

Course duration

Course structure

• Introduction
• HDL design flow
• History of VHDL
• Structural HDL
• Behavioral HDL description
• Hands-on Practical 1: Introduction to Quartus II
• Basic VHDL 1
• Language constructs
• Data types and representation
• Component instantiation
• Concurrent statements
• Operators
• Multiplexers
• Hands-on Practical 2: Combinational Logic
• Basic VHDL 2
• Concatenation
• Repetition
• Aggregates and array slices
• Enumeration
• RAMs and ROMs
• Hands-on Practical 3: Seven Segment Decoder
• Sequential Design
• Register basics
• Sequential statements
• Blocking assignments
• Registers, latches and counters
• Hands-on Practical 4: Up/Down Counter
• Modularisation
• Hierarchical design
• Parameterization
• Generation
• Hands-on Practical 5: Real-time Clock
• State Machine
• Registers transfer operations
• Algorithmic State Machine
• Hands-on Practical 6: Serial Transceiver (Transmission)
• Testbenches
• Introduction
• Testbench methods
• Hands-on Practical 7: ModelSim-Altera Simulations
• Hands-on Practical 8: Serial Transceiver (Reception)

Instructor

Course Schedule

Consultancy

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  Tel: +603 03 5889 5889

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