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Verilog: Small and FastCourse id: 0028 SynopsisA hardware description language (HDL) is a language for formal description and design of electronic circuits, and most-commonly, digital logic. It can describe the circuit's operation, its design and organization, and tests to verify its operation by means of simulation.In traditional chip design, there is the classic trade-off between clock speed and chip area size. As HDL designers are focused on functionality, there may be a tendency to write bad HDL code and depend on the synthesis tool to constrain the area and speed of the final hardware. There is a better way however, that is to write optimal HDL that will result in hardware that is both small and fast – having your cake and eating it too! This course uses Verilog, though it can be tailored for VHDL.
Course highlight Xilinx ISE and other tools will be used for this purpose. What you will learnThis course comprises of the following main topics:
Who should attendThis course is particularly suited for engineers responsible for designing and implementing digital chip-design systems.PrerequisiteParticipants must be familiar with synthesisable Verilog at the RTL level.Course methodologyThis course is presented in a workshop style with example-led lectures interlaced with hands-on practical for maximum understanding.Course duration3 days.Course structure
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