Training Courses

Advanced FPGA Interfacing and Optimisation

Course id: 0032

Synopsis

The digital age heralds the need for vast data processing and number crunching capabilities to satisfy our insatiable needs. Applications such as video compression/ decompression, voice recognition and 3D graphics typically required electronic devices to incorporate some form of hardware acceleration to produce the required processing throughput.

This course covers advanced FPGA interfacing with DDR2/3 memory; and optimization techniques such as loop unrolling, pipelining, chaining and multicycling.

Course highlight
Participants would have hands-on experience using the Altera DE2 Developmet Kit and the Quartus II design environment.

What you will learn

This course concentrates on the theoretical and practical knowledge covering the following main topics:

Interfacing DDR memory
Loop unrolling
Pipelining
Chaining
Multicycling

Who should attend

Engineers and researchers who are developing and optimising FPGA-based systems.

Prerequisite

Participants have to be familiar with Verilog and FPGA-based development.

Course methodology

This course is presented in a workshop style with lectures interlaced with demonstrations and hands-on practical sessions for maximum understanding.

Course duration

4 days.

Course structure

DDR Memory
- Overview
- Specification
- Timing parameters
- Command set
DDR SDRAM Controller
- Introduction
- Reading and writing RAM
- Hands-on practical 1: Reading and Writing SDRAM
- Advanced controller functions
- Hands-on practical 2: Advanced DDR SDRAM Control
Memory Optimisation
- Storage strategies for optimised DDR RAM access
- Hands-on practical 3: Optimising DDR RAM Storage
Computation Optimisation
- Overview of optimization techniques
- Parallelism with loop unrolling
- Hands-on practical 4: Loop Unrolling
- Pipelining strategies
- Data forwarding
- Hazard detection
- Hands-on practical 5: Pipelining to Increase Throughput
- Chaining
- Hands-on practical 6: Chaining for Balanced Pipeline
- Multicycling
- Hands-on practical 7: Multicycling to Hide Latency

Instructor

Dr Royan Ong

Course Schedule

Consultancy

Technical Consultancy

News on ProvenPac

ProvenPac is HRDF Certified

  ProvenPac Sdn. Bhd.
  C-4-3 Gembira Park,
  Jalan Riang, 58200
  Kuala Lumpur, Malaysia

Tel: +603 03 5889 5889

No public course
currently scheduled.

Please inform me when
this course is scheduled.

Please contact me to
arrange in-house training.

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