Training Courses

Implementing Digital Signal Processing on FPGAs

Course id: 0052

Synopsis

Digital signal processing (DSP) is the backbone of numerous technological fields, such as wired and wireless communication, military and intelligence gathering, industrial process control, medical science, cryptography and transportation. DSP algorithms such as spectral analysis and Kalman filtering â€” traditionally executed with specialised digital signal processors â€” are now increasingly carried out with FPGAs for their greater processing capabilities, increased chip-level integration and lower power consumption. The move towards FPGAs also mean DSP algorithms are now coded in hardware description languages rather than assembly, C or C++.

This course concentrates on the implementation of DSP techniques natively in hardware using VHDL. Participants would be introduced to floating point arithmetic in hardware, DSP hardware patterns, followed by parallelism and pipelining optimisation techniques for implementing high speed and/or low power/footprint digital systems.

Course highlight
Participants will have practical design experience using industry-standard logic simulators (Synopsys VCS-MX), logic synthesis tools (Synopsys Design Compiler, Xilinx Vivado or Altera Quartus), and development boards from Altera or Xilinx.

What you will learn

This course concentrates on the theoretical and practical knowledge to allow participants to achieve the following learning outcomes. Upon completing the course, participants would be able to:

Understand the relationship between software coding and hardware implementation
Convert software code to synthesizable hardware
Implement DSP algorithms on FPGAs with VHDL
Maximising computation speed through parallelism and pipelining

Who should attend

This course is particularly suited for engineers involved in DSP development interested in using the HDL digital design and verification flow.

Prerequisite

Participants should have a degree in electronics (and related) engineering with an understanding of digital systems and FPGA implementation with VHDL/Verilog. Working knowledge on DSP theory is required for this programme.

Course methodology

This course is presented in a workshop style with example-led lectures interlaced with demonstrations and hands-on practical for maximum understanding.

Course duration

3 days.

Course structure

Introduction
- Brief overview of digital signal processing
- Number storage and representation formats
FIR filter simulation
- Setting up Synopsys VCS-MX simulator
- Simulation flow
- Hands-on Practical 1: Simulating an FIR Filter
FIR filter synthesis
- Setting up Synopsys Design Compiler and Xilinx Vivado/Altera Quartus
- Representing filters with block diagrams
- From block diagrams to hardware
- Shift registers, multipliers and adders
- Developing the control unit
- Hands-on Practical 2: Synthesis of an FIR Filter
FPGA implementation
- Setting up Xilinx Vivado/Altera Quartus auto-placement-and-routing (APR), chip floorplanning, and design assembly tools
- Hands-on Practical 3: FPGA Implementation of an FIR Filter
FIR filter verification
- Overview of the development board, clock and reset assignments, JTAG set-up
- Setting up Xilinx ChipScope Pro/Altera SignalTap II
- Hands-on Practical 4: Verifying the FIR Filter
Optimising for speed
- Overview of pipelining
- Pipelining the datapath
- Hands-on Practical 5: Pipelined FIR Filter
Implementing an IIR filter
- Overview of IIR filters
- Hands-on Practical 6: Implementing Optimised IIR Filters

Course Schedule

Consultancy

Technical Consultancy

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  C-4-3 Gembira Park,
  Jalan Riang, 58200
  Kuala Lumpur, Malaysia

Tel: +603 03 5889 5889

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