Training Courses

Fundamentals of RISC Processor Architecture

Course id: 0059

Synopsis

The digital age heralds the need for vast data processing and number crunching capabilities to satisfy our insatiable needs. Applications such as video compression/ decompression, voice recognition and 3D graphics typically required electronic devices to incorporate some form of hardware acceleration to produce the required processing throughput.

This course covers the essential concepts of RISC processing such as the instruction set, ALU, registers, Control Unit, data transfers and branching operations.

Course highlight
Participants will have practical design experience using the Altera DE2 FPGA development board, together with the use of Alteraâ€™s Quartus II development software. They will, at the end of the course, complete a MIPS-like processor.

What you will learn

This course concentrates on the theoretical and practical knowledge to allow participants to achieve the following learning outcomes. Upon completing the course, participants would be able to:

Understand the fundamentals of RISC processor architectures
Understand the relationship between programs, machine code and the hardware
Implement arithmetic and logical functions in hardware
Develop a simple MIPS-like processor

Who should attend

This course is particularly suited for engineers involved in the design of processors or processing cores to achieve high processing speeds.

Prerequisite

Participants should have a diploma/degree in electronics (and related) engineering with an understanding of digital systems. They must have the knowledge of developing synthesizable hardware in Verilog, and have an understanding of algorithmic state machines (ASM).

Course methodology

This course is presented in a workshop style with lectures interlaced with demonstrations and hands-on practicals for maximum understanding.

Course duration

2 days.

Course structure

Introduction
- Harvard vs Von Neumann
- CISC vs RISC
- The MIPS architecture
Core MIPS
- Registers
- Hands-on practical 1: Implementing the Register File
- Adders/subtractors
- Logical operations
- Shifts and rotates
- Hands-on practical 2: Developing the ALU
Executing Instructions
- Instruction cycle
- Control Unit
- Hands-on practical 3: Processor Control
Memory Access
- Data operations
- Data transfer
- Hands-on practical 4: Memory Access
Branching
- Relative and absolute jumps
- Conditional branching
- Hands-on practical 5: Program Branching

Instructor

Dr Royan Ong

Course Schedule

Consultancy

Technical Consultancy

News on ProvenPac

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  ProvenPac Sdn. Bhd.
  C-4-3 Gembira Park,
  Jalan Riang, 58200
  Kuala Lumpur, Malaysia

Tel: +603 03 5889 5889

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